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integrated synthesizer and vco data sheet adf4360-0 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2012 analog devices, inc. all rights reserved. features output frequency range: 2400 mhz to 2725 mhz divide-by-2 output 3.0 v to 3.6 v power supply 1.8 v logic compatibility integer-n synthesizer programmable dual-modulus prescaler 16/17, 32/33 programmable output power level 3-wire serial interface analog and digital lock detect hardware and software power-down mode applications wireless handsets (dect, gsm, pcs, dcs, wcdma) test equipment wireless lans catv equipment general description the adf4360-0 is a fully integrated integer-n synthesizer and voltage-controlled oscillator (vco). the adf4360-0 is designed for a center frequency of 2600 mhz. in addition, a divide-by-2 option is available, whereby the user gets an rf output of between 1200 mhz and 1360 mhz. control of all the on-chip registers is through a simple 3-wire interface. the device operates with a power supply ranging from 3.0 v to 3.6 v and can be powered down when not in use. functional block diagram muxout cp v vco ref in clk data le av dd dv dd ce agnd dgnd cpgnd r set v tune c c c n rf out a rf out b vco core phase comparator mute divsel = 2 divsel = 1 n = (bp + a) load load charge pump output stage multiplexer integer register 13-bit b counter 14-bit r counter 24-bit function latch 24-bit data register 5-bit a counter prescaler p/p+1 multiplexer lock detect 2 adf4360-0 04644-001 figure 1.
adf4360-0 data sheet rev. b | page 2 of 24 table of contents specifications ..................................................................................... 3 ? timing characteristics ..................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? transistor count ........................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? circuit description ........................................................................... 9 ? reference input section ............................................................... 9 ? prescaler (p/p + 1) ........................................................................ 9 ? a and b counters ......................................................................... 9 ? r counter ...................................................................................... 9 ? pfd and charge pump ................................................................ 9 ? muxout and lock detect ...................................................... 10 ? input shift register ..................................................................... 10 ? vco ............................................................................................. 10 ? output stage ................................................................................ 11 ? latch structure ........................................................................... 12 ? power-up ..................................................................................... 16 ? control latch .............................................................................. 18 ? n counter latch ......................................................................... 19 ? r counter latch ......................................................................... 19 ? applications ..................................................................................... 20 ? fixed frequency lo ................................................................... 20 ? interfacing ................................................................................... 20 ? pcb design guidelines for chip scale package ........................... 21 ? output matching ........................................................................ 21 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 22 ? revision history 2/12rev. a to rev. b changes to figure 3 and table 4..................................................... 7 updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 22 12/04rev. 0 to rev. a updated format..................................................................universal changes to timing characteristics ................................................ 5 changes to power-up section ...................................................... 16 added table 10 ............................................................................... 16 added figure 16.............................................................................. 16 changes to ordering guide .......................................................... 22 updated outline dimensions ....................................................... 22 7/04revision 0: initial version
data sheet adf4360-0 rev. b | page 3 of 24 specifications 1 av dd = dv dd = v vco = 3.3 v 10%; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. table 1. parameter b version unit conditions/comments ref in characteristics ref in input frequency 10/250 mhz min/max for f < 10 mhz, use dc-coupled cmos-compatible square wave, slew rate > 21 v/s. ref in input sensitivity 0.7/av dd v p-p min/max ac-coupled. 0 to av dd v max cmos-compatible. ref in input capacitance 5.0 pf max ref in input current 100 a max phase detector phase detector frequency 2 8 mhz max charge pump i cp sink/source 3 with r set = 4.7 k. high value 2.5 ma typ low value 0.312 ma typ r set range 2.7/10 k i cp three-state leakage current 0.2 na typ sink and source current matching 2 % typ 1.25 v v cp 2.5 v. i cp vs. v cp 1.5 % typ 1.25 v v cp 2.5 v. i cp vs. temperature 2 % typ v cp = 2.0 v. logic inputs v inh , input high voltage 1.5 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in , input capacitance 3.0 pf max logic outputs v oh , output high voltage dv dd C 0.4 v min cmos output chosen. i oh , output high current 500 a max v ol , output low voltage 0.4 v max i ol = 500 a. power supplies av dd 3.0/3.6 v min/v max dv dd av dd v vco av dd ai dd 4 10 ma typ di dd 4 2.5 ma typ i vco 4 , 5 19.0 ma typ i core = 10 ma. i rfout 4 3.5 to 11.0 ma typ rf o utput stage is programmable. low power sleep mode 4 7 a typ rf output characteristics 5 vco output frequency 2400/2725 mhz min/max i core = 15 ma. vco sensitivity 56 mhz/v typ lock time 6 250 s typ to within 10 hz of final frequency. frequency pushing (open-loop) 1 mhz/v typ frequency pulling (open-loop) 15 khz typ into 2.00 vswr load. harmonic content (second) ?30 dbc typ harmonic content (third) ?39 dbc typ output power 5 , 7 ?13/?6.5 dbm typ programmable in 3 db steps. see table 7 . output power variation 3 db typ for tuned loads, see the output matching section. vco tuning range 1.25/2.50 v min/max vco tuning port leakage current 0.2 na typ
adf4360-0 data sheet rev. b | page 4 of 24 parameter b version unit conditions/comments noise characteristics 5 vco phase-noise performance 8 ?111 dbc/hz typ @ 100 khz offset from carrier. ?133 dbc/hz typ @ 1 mhz offset from carrier. ?140 dbc/hz typ @ 3 mhz offset from carrier. ?145 dbc/hz typ @ 10 mhz offset from carrier. synthesizer phase-noise floor 9 ?172 dbc/hz typ @ 25 khz pfd frequency. ?163 dbc/hz typ @ 200 khz pfd frequency. ?147 dbc/hz typ @ 8 mhz pfd frequency. in-band phase noise 10 , 11 ?80 dbc/hz typ @ 1 khz offset from carrier. rms integrated phase error 12 1.4 degrees typ 100 hz to 100 khz. spurious signals due to pfd frequency 11, 13 ?75 dbc typ level of unlocked signal with mtld enabled ?45 dbm typ 1 operating temperature range is: C40c to +85c. 2 guaranteed by design. sample tested to ensure compliance. 3 i cp is internally modified to maintain constant loop gain over the frequency range. 4 t a = 25c; av dd = dv dd = v vco = 3.3 v; p = 32. 5 these characteristics are guarant eed for vco core power = 10 ma. 6 jumping from 2.4 ghz to 2.725 ghz. pfd fr equency = 200 khz; loop bandwidth = 10 khz. 7 using 50 resistors to v vco into a 50 load. for tuned loads, see the output matching section. 8 the noise of the vco is meas ured in open-loop conditions. 9 the synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0 log n (where n is the n divider value). 10 the phase noise is measured with the eval-adf4360- xeb1 evaluation board an d the hp8562e spectrum analyzer. the spectrum analyz er provides the ref in for the synthesizer; offset frequency = 1 khz. 11 f refin = 10 mhz; f pfd = 200 khz; n = 2600; loop b/w = 10 khz. 12 f refin = 10 mhz; f pfd = 1 mhz; n = 2600; loop b/w = 25 khz. 13 the spurious signals are meas ured with the eval-adf4360- xeb1 evaluation board and the hp8562e spectrum analyzer. the spectrum analyzer provides the ref in for the synthesizer; f refout = 10 mhz @ 0 dbm.
data sheet adf4360-0 rev. b | page 5 of 24 timing characteristics 1 av dd = dv dd = v vco = 3.3 v 10%; agnd = dgnd = 0 v; 1.8 v and 3 v logic levels used; t a = t min to t max , unless otherwise noted. table 2. parameter limit at t min to t max (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le setup time t 7 20 ns min le pulse width 1 see the section for the recomme nded power-up procedure for this device. power-up cloc k data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 04644-002 figure 2. timing diagram
adf4360-0 data sheet rev. b | page 6 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd 1 ?0.3 v to +3.9 v av dd to dv dd ?0.3 v to +0.3 v v vco to gnd ?0.3 v to +3.9 v v vco to av dd ?0.3 v to +0.3 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v dd + 0.3 v ref in to gnd ?0.3 v to v dd + 0.3 v operating temperature range ?40c to + 85c storage temperature range ?65c to +150c maximum junction temperature 150c csp ja thermal impedance paddle soldered 50c/w paddle not soldered 88c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 gnd = agnd = dgnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those included in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <1 kv and it is esd sensitive. proper precautions should be taken for handling and assembly. transistor count 12543 (cmos) and 700 (bipolar). esd caution
data sheet adf4360-0 rev. b | page 7 of 24 pin configuration and fu nction descriptions adf4360-0 top view (not to scale) cpgnd notes 1. the exposed pad must be connected to agnd. 1 av dd 2 agnd 3 rf out a 4 rf out b 5 v vco 6 data 18 clk 17 ref in 16 dgnd 15 c n 14 r set 13 v tune 7 agnd 8 agnd 9 agnd 10 agnd 11 c c 12 cp 24 ce 23 agnd 22 dv dd 21 muxout 20 le 19 04644-003 pin 1 identifier figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic function 1 cpgnd charge pump ground. this is the ground return path for the charge pump. 2 av dd analog power supply. this ranges from 3.0 v to 3.6 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must have the same value as dv dd . 3, 8 to 11, 22 agnd analog ground. this is the ground return path of the prescaler and vco. 4 rf out a vco output. the output level is programma ble from ?6.5 dbm to ?13 dbm. see the output matching section for a description of the various output stages. 5 rf out b vco complementary output. the output level is programmable from ?6.5 dbm to ?13 dbm. see the output matching section for a description of the various output stages. 6 v vco power supply for the vco. this ranges from 3.0 v to 3.6 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. v vco must have the same value as av dd . 7 v tune control input to the vco. this voltage determines the ou tput frequency and is derived from filtering the cp output voltage. 12 c c internal compensation node. this pin must be decoupled to ground with a 10 nf capacitor. 13 r set connecting a resistor between this pin and cp gnd sets the maximum charge pump output current for the synthesizer. the nominal voltage potential at the r set pin is 0.6 v. the relationship between i cp and r set is set cpmax r i = where r set = 4.7 k, i cpmax = 2.5 ma. 14 c n internal compensation node. th is pin must be decoupled to v vco with a 10 f capacitor. 15 dgnd digital ground. 16 ref in reference input. this is a cmos input with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k. see figure 10 . this input can be driven from a ttl or cmos crystal oscillator or it can be ac-coupled. 17 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into th e 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. 18 data serial data input. the serial data is loaded msb firs t with the two lsbs being the control bits. this input is a high impedance cmos input. 19 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, and the relevant latch is selected using the control bits. 20 muxout this multiplexer output allows either the lock detect , the scaled rf, or the scaled reference frequency to be access ed externally. 21 dv dd digital power supply. this ranges from 3.0 v to 3.6 v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must have the same value as av dd . 23 ce chip enable. a logic low on this pin powers down th e device and puts the charge pump into three-state mode. taking the pin high powers up the device depe nding on the status of the power-down bits. 24 cp charge pump output. when enabled, this provides i cp to the external loop filter, wh ich in turn, drives the internal vco. ep exposed pad. the exposed pad must be connected to agnd.
adf4360-0 data sheet rev. b | page 8 of 24 typical performance characteristics 04644-004 ?150 ?160 ?170 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?40 ?50 ?60 ?30 ?20 ?10 0 1k 10m 1m 100k 10k frequency offset (hz) 4 3 2 1 output power (db) figure 4. open-loop vco phase noise 04644-005 ?145 ?150 ?140 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ?90 ?95 ?100 ?85 ?80 ?75 ?70 100 10m 1m 100k 10k 1000 frequency offset (hz) output power (db) figure 5. vco phase noise, 2600 mhz, 200 khz pfd, 10 khz loop bandwidth 04644-006 ?145 ?150 ?140 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ?90 ?95 ?100 ?85 ?80 ?75 ?70 100 10m 1m 100k 10k 1000 frequency offset (hz) output power (db) figure 6. vco phase noise, 1300 mhz, divide-by-2 enabled, 200 khz pfd, 10 khz loop bandwidth 04644-007 output power (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?2khz ?1khz 2600mhz 1khz 2khz ?80.4dbc/hz v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz res. bandwidth = 30hz video bandwidth = 30hz sweep = 1.9 seconds averages = 20 reference level = ?3.5dbm figure 7. close-in phase noise at 2600 mhz (200 khz channel spacing) 04644-008 output power (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?0.25mhz ?0.1mhz 2600mhz 0.1mhz 0.25mhz ?77dbc reference level = ?6dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz res. bandwidth = 1khz video bandwidth = 1khz averages = 20 figure 8. reference spurs at 2600 mhz (200 khz channel spacing, 10 khz loop bandwidth) 04644-009 output power (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?1mhz ?0.5mhz 2250mhz 0.5mhz 1mhz ?86dbc/hz v dd = 3v, v vco = 3v i cp = 2.5ma pfd frequency = 1mhz loop bandwidth = 25khz res. bandwidth = 10khz video bandwidth = 10khz sweep = 1.9 seconds averages = 10 figure 9. reference spurs at 2600 mhz (1 mhz channel spacing, 25 khz loop bandwidth)
data sheet adf4360-0 rev. b | page 9 of 24 circuit description reference input section the reference input stage is shown in figure 10 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed, and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. 04644-010 buffer to r counter ref in 100k nc sw2 sw3 no nc sw1 power-down control figure 10. reference input stage prescaler (p/p + 1) the dual-modulus prescaler (p/p + 1), along with the a and b counters, enables the large division ratio, n , to be realized (n = bp + a). the dual-modulus prescaler, operating at cml levels, takes the clock from the vco and divides it down to a manageable frequency for the cmos a and b counters. the prescaler is programmable. it can be set in software to 8/9, 16/17, or 32/33 and is based on a synchronous 4/5 core. there is a minimum divide ratio possible for fully contiguous output frequencies; this minimum is determined by p, the prescaler value, and is given by (p 2 ? p). a and b counters the a and b cmos counters combine with the dual-modulus prescaler to allow a wide range division ratio in the pll feedback counter. the counters are specified to work when the prescaler output is 300 mhz or less. thus, with a vco frequency of 2.5 ghz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid. pulse swallow function the a and b counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the vco frequency equation is () rfabpf refin vco /]+[= where: f vco is the output frequency of the vco. p is the preset modulus of the dual-modulus prescaler (8/9, 16/17, and so on). b is the preset divide ratio of the binary 13-bit counter (3 to 8191). a is the preset divide ratio of the binary 5-bit swallow counter (0 to 31). f refin is the external reference frequency oscillator. n = bp + a to pfd from vco n divider modulus control load load 13-bit b counter 5-bit a counter prescaler p/p+1 04644-011 figure 11. a and b counters r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. pfd and charge pump the pfd takes inputs from the r counter and n counter (n = bp + a) and produces an output proportional to the phase and frequency difference between them. figure 12 is a simplified schematic. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. two bits in the r counter latch, abp2 and abp1, control the width of the pulse (see table 9 ). 04644-012 programmable delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 abp1 abp2 r divider n divider c p output r divider n divider cp cpgnd v p figure 12. pfd simplified schematic and timing (in lock)
adf4360-0 data sheet rev. b | page 10 of 24 muxout and lock detect the output multiplexer on the adf4360 family allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the function latch. the full truth table is shown in table 7 . figure 13 shows the muxout section in block diagram form. lock detect muxout can be programmed for two types of lock detect: digital and analog. digital lock detect is active high. when ldp in the r counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. with ldp set to 1, five consecutive cycles of less than 15 ns phase error are required to set the lock detect. it stays set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. the n-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k nominal. when a lock has been detected, this output is high with narrow low-going pulses. r counter output n counter output digital lock detect dgnd control mux muxout dv dd analog lock detect sdout 04644-013 figure 13. muxout circuit input shift register the adf4360 familys digital section includes a 24-bit input shift register, a 14-bit r counter, and an 18-bit n counter, comprised of a 5-bit a counter and a 13-bit b counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in figure 2 . the truth table for these bits is shown in table 5 . table 6 shows a summary of how the latches are programmed. note that the test mode latch is used for factory testing and should not be programmed by the user. table 5. c2 and c1 truth table control bits c2 c1 data latch 0 0 control latch 0 1 r counter 1 0 n counter (a and b) 1 1 test mode latch vco the vco core in the adf4360 family uses eight overlapping bands, as shown in figure 14 , to allow a wide frequency range to be covered without a large vco sensitivity (k v ) and resultant poor phase noise and spurious performance. the correct band is chosen automatically by the band select logic at power-up or whenever the n counter latch is updated. it is important that the correct write sequence be followed at power-up. this sequence is 1. r counter latch 2. control latch 3. n counter latch during band select, which takes five pfd cycles, the vco v tune is disconnected from the output of the loop filter and connected to an internal reference voltage. 04644-014 0.5 0.7 0.9 1.1 1.3 1.5 1.9 2.1 2.3 1.7 2.5 voltage (v) frequency (mhz) 2200 2400 2600 2800 3000 figure 14. frequency vs. v tune , adf4360-0 the r counter output is used as the clock for the band select logic and should not exceed 1 mhz. a programmable divider is provided at the r counter input to allow division by 1, 2, 4, or 8 and is controlled by bits bsc1 and bsc2 in the r counter latch. where the required pfd frequency exceeds 1 mhz, the divide ratio should be set to allow enough time for correct band selection. after band select, normal pll action resumes. the nominal value of k v is 56 mhz/v or 28 mhz/v, if divide-by-2 operation has been selected (by programming div2 [db22] high in the n counter latch). the adf4360 family contains linearization circuitry to minimize any variation of the product of i cp and k v .
data sheet adf4360-0 rev. b | page 11 of 24 the operating current in the vco core is programmable in four steps: 5 ma, 10 ma, 15 ma, and 20 ma. this is controlled by bits pc1 and pc2 in the control latch. if the outputs are used individually, the optimum output stage consists of a shunt inductor to v dd . another feature of the adf4360 family is that the supply current to the rf output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. this is enabled by the mute-till-lock detect (mtld) bit in the control latch. output stage the rf out a and rf out b pins of the adf4360 family are connected to the collectors of an npn differential pair driven by buffered outputs of the vco, as shown in figure 15 . to allow the user to optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable via bits pl1 and pl2 in the control latch. four current levels may be set: +3.5 ma, +5 ma, +7.5 ma, and +11 ma. these levels give output power levels of ?13 dbm, ?11 dbm, ?8.5 dbm, and ?6.5 dbm, respectively, using a 50 resistor to v dd and ac coupling into a 50 load. alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180 microstrip coupler (see the output matching section). vco rf out arf out b buffer/ divide by 2 04644-015 figure 15. output stage adf4360-0
adf4360-0 data sheet rev. b | page 12 of 24 latch structure table 6 shows the three on-chip latches for the adf4360 family. the two lsbs determine which latch is programmed. table 6. latch structure db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2crm1m2 pdp cpcpg mtld pl1pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 m3 control bits muxout control current setting 2 current setting 1 prescaler value core power level output power level db21 db22 db23 power- down 2 power- down 1 counter reset mute-till- ld cp gain cp three- state phase detector polarity pd2p1p2 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1r2r3r4r5 r7r8r9r10 r11r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 control bits band select clock anti- backlash pulse width 14-bit reference counter db21 db22 db23 lock detect precision test mode bit reserved reserved divide- by-2 divide-by- 2 select bsc2 rsv rsv db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1a2a3a4a5 b1b2b3b4b5b6b7b8b9b10 b11 b12 b13 rsv control bits 5-bit a counter 13-bit b counter control latch n counter latch r counter latch db21 db22 db23 cp gain reserved cpg div2 divsel 04644-016
data sheet adf4360-0 rev. b | page 13 of 24 table 7. control latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2crm1m2 pdp cpcpg mtld pl1pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 m3 control bits muxout control current setting 2 current setting 1 prescaler value core power level output power level db21 db22 db23 power- down 2 power- down 1 counter reset mute-till- ld cp gain cp three- state phase detector polarity pd2p1p2 cr 0 1 counter operation normal r, a, b counters held in reset pc2 0 0 10 core power level 5ma 10ma 15ma pc1 0 1 11 20ma cp 0 1 charge pump output normal three-state pdp 0 1 phase detector polarity negative positive cpg 0 1 cp gain current setting 1 current setting 2 mtld 0 1 mute-till-lock detect disabled enabled m3 m2 m1 output three-state output 000 001 010 011 100 101 110 111 digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect serial data output dgnd p2 p1 prescaler value 0 0 8/9 0 1 16/17 1 0 32/33 1 1 32/33 ce pin pd2 pd1 mode 0 x x asynchronous power-down 1 x 0 normal operation 1 0 1 asynchronous power-down 1 1 1 synchronous power-down cpi6 cpi5 cpi4 i cp (ma) cpi3 cpi2 cpi1 4.7k 0.31 0.62 0.93 1.25 1.56 1.87 2.18 2.50 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 pl2 pl1 output power level current power into 50 (using 50 to v vcc ) ?13 dbm ?11 dbm ? 8dbm ? 6dbm 0 0 1 1 0 1 0 1 3.5ma 5.0ma 7.5ma 11.0ma 04644-017
adf4360-0 data sheet rev. b | page 14 of 24 table 8. n counter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1a2a3a4a5 b1b2b3b4b5b6b7b8b9b10 b11 b12 b13 rsv control bits 5-bit a counter 13-bit b counter db21 db22 db23 cp gain divide-by- 2 select divide- by-2 reserved cpg div2 divsel this bit is not used by the device and is a don't care bit. a5 a4 .......... a2 a1 a counter divide ratio 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 28 1 1 .......... 0 1 29 1 1 .......... 1 0 30 1 1 .......... 1 1 31 f4 (function latch) fastlock enable cp gain operation charge pump current setting 1 is permanently used 0 0 charge pump current setting 2 is permanently used 1 0 n = bp + a; p is prescaler value set in the control latch. b must be greater than or equal to a. for continuously adjacent values of (n f ref ), at the output, n min is (p 2 ?p). b13 b12 b11 b3 b2 b1 b counter divide ratio .......... 0 00 0 00 0 00 0 00 0 0 0 not allowed .......... 0 0 1 not allowed .......... 0 1 0 not allowed .......... 1 1 1 3 .......... . .. . .. . .. . .. . .......... . . . . .......... . . . . .......... 1 11 1 11 1 11 1 11 1 0 0 8188 .......... 1 0 1 8189 .......... 1 1 0 8190 .......... 1 1 1 8191 04644-018 div2 0 1 divide-by-2 fundamental output divide-by-2 divsel 0 1 divide-by-2 select (prescaler input) fundamental output selected divide-by-2 selected
data sheet adf4360-0 rev. b | page 15 of 24 table 9. r counter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1r2r3r4r5 r7r8r9r10 r11r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 control bits band select clock anti- backlash pulse width 14-bit reference counter db21 db22 db23 lock detect precision test mode bit reserved reserved bsc2 rsv rsv test mode bit should be set to 0 for normal operation. r14 r13 r12 r3 r2 r1 divide ratio .......... 0 00 0 00 0 00 0 00 0 00 1 .......... 0 1 1 2 .......... 0 1 0 3 .......... 1 0 1 4 .......... . .. . .. . .. . .. . .......... . . . . .......... . . . . .......... 1 11 1 11 1 11 1 11 1 0 0 16380 .......... 1 0 1 16381 .......... 1 1 0 16382 .......... 1 1 1 16383 these bits are not used by the device and are don't care bits. 04644-019 ldp lock detect precision 0 three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 1 five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. abp2 abp1 antibacklash pulse width 0 0 3.0ns 0 1 1.3ns 1 0 6.0ns 1 1 3.0ns bsc2 bsc1 band select clock divider 001 01 2 104 118
adf4360-0 data sheet rev. b | page 16 of 24 power-up power-up sequence the correct programming sequence for the adf4360-0 after power-up is: 1. r counter latch 2. control latch 3. n counter latch initial power-up initial power-up refers to programming the part after the application of voltage to the av dd , dv dd , v vco , and ce pins. on initial power-up, an interval is required between programming the control latch and programming the n counter latch. this interval is necessary to allow the transient behavior of the adf4360-0 during initial power-up to have settled. during initial power-up, a write to the control latch powers up the part and the bias currents of the vco begin to settle. if these currents have not settled to within 10% of their steady-state value and if the n counter latch is then programmed, the vco may not be able to oscillate at the desired frequency, which does not allow the band select logic to choose the correct frequency band and the adf4360-0 may not achieve lock. if the recommended interval is inserted and the n counter latch is programmed, the band select logic can choose the correct frequency band and the part locks to the correct frequency. this duration of this interval is affected by the value of the capacitor on the c n pin (pin 14). this capacitor is used to reduce the close-in noise of the adf4360-0 vco. the recommended value of this capacitor is 10 f. using this value requires an interval of 5 ms between the latching in of the control latch bits and latching in of the n counter latch bits. if a shorter delay is required, this capacitor can be reduced. a slight phase noise penalty is incurred by this change, which is explained further in tabl e 10 . table 10. c n capacitance vs. interval and phase noise c n value recommended interval between control latch and n counter latch open loop phase noise @ 10 khz offset 10 f 5 ms ?84 dbc 440 nf 600 s ?82 dbc clock power-up data le r counter latch data control latch data n counter latch data required interval control latch write to n counter latch write 04644-020 figure 16. adf4360-0 power-up timing
data sheet adf4360-0 rev. b | page 17 of 24 hardware power-up/power-down if the adf4360-0 is powered down via the hardware (using the ce pin) and powered up again without any change to the n counter register during power-down, it locks at the correct frequency because the part is already in the correct frequency band. the lock time depends on the value of capacitance on the c n pin, which is <5 ms for 10 f capacitance. the smaller capacitance of 440 nf on this pin enables lock times of <600 s. the n counter value cannot be changed while it is in power- down because the part may not lock to the correct frequency on power-up. if it is updated, the correct programming sequence for it after power-up is to the r counter latch, followed by the control latch, and finally the n counter latch, with the required interval between the control latch and n counter latch, as described in the initial power-up section. software power-up/power-down if the adf4360-0 is powered down via the software (using the control latch) and powered up again without any change to the n counter latch during power-down, it locks at the correct frequency because it is already in the correct frequency band. the lock time depends on the value of capacitance on the c n pin, which is <5 ms for 10 f capacitance. the smaller capacitance of 440 nf on this pin enables lock times of <600 s. the n counter value cannot be changed while it is in power- down because the part may not lock to the correct frequency on power-up. if it is updated, the correct programming sequence for it after power-up is to the r counter latch, followed by the control latch, and finally the n counter latch, with the required interval between the control latch and n counter latch, as described in the initial power-up section.
adf4360-0 data sheet rev. b | page 18 of 24 control latch with (c2, c1) = (0, 0), the control latch is programmed. table 7 shows the input data format for programming the control latch. prescaler value in the adf4360 family, p2 and p1 in the control latch set the prescaler values. power-down db21 (pd2) and db20 (pd1) provide programmable power- down modes. in the programmed asynchronous power-down, the device powers down immediately after latching a 1 into bit pd1, with the condition that pd2 has been loaded with a 0. in the programmed synchronous power-down, the device power- down is gated by the charge pump to prevent unwanted frequency jumps. once the power-down is enabled by writing a 1 into bit pd1 (on the condition that a 1 has also been loaded to pd2), the device goes into power-down on the second rising edge of the r counter output, after le goes high. when the ce pin is low, the device is immediately disabled regardless of the state of pd1 or pd2. when a power-down is activated (either synchronous or asynchronous mode), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital lock detect circuitry is reset. ? the rf outputs are debiased to a high impedance state. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. charge pump currents cpi3, cpi2, and cpi1 in the adf4360 family determine current setting 1. cpi6, cpi5, and cpi4 determine current setting 2. see the truth table in table 7 . output power level bits pl1 and pl2 set the output power level of the vco. see the truth table in table 7 . mute-till-lock detect db11 of the control latch in the adf4360 family is the mute-till- lock detect bit. this function, when enabled, ensures that the rf outputs are not switched on until the pll is locked. cp gain db10 of the control latch in the adf4360 family is the charge pump gain bit. when it is programmed to a 1, current setting 2 is used. when it is programmed to a 0, current setting 1 is used. charge pump three-state this bit puts the charge pump into three-state mode when programmed to a 1. it should be set to 0 for normal operation. phase detector polarity the pdp bit in the adf4360 family sets the phase detector polarity. the positive setting enabled by programming a 1 is used when using the on-chip vco with a passive loop filter or with an active non-inverting filter. it can also be set to 0. this is required, if an active inverting loop filter is used. muxout control the on-chip multiplexer is controlled by m3, m2, and m1. see the truth table in table 7 . counter reset db4 is the counter reset bit for the adf4360 family. when this is 1, the r counter and the a, b counters are reset. for normal operation, this bit should be 0. core power level pc1 and pc2 set the power level in the vco core. the recommended setting is 10 ma. see the truth table in table 7 .
data sheet adf4360-0 rev. b | page 19 of 24 n counter latch with (c2, c1) = (1, 0), the n counter latch is programmed. table 8 shows the input data format for programming the n counter latch. a counter latch a5 to a1 program the 5-bit a counter. the divide range is 0 (00000) to 31 (11111). reserved bits db7 is a spare bit that is reserved. it should be programmed to 0. b counter latch b13 to b1 program the b counter. the divide range is 3 (00.....0011) to 8191 (11....111). overall divide range the overall divide range is defined by ((p b) + a), where p is the prescaler value. cp gain db21 of the n counter latch in the adf4360 family is the charge pump gain bit. when this is programmed to 1, current setting 2 is used. when programmed to 0, current setting 1 is used. this bit can also be programmed through db10 of the con- trol latch. the bit always reflects the latest value written to it, whether this is through the control latch or the n counter latch. divide-by-2 db22 is the divide-by-2 bit. when set to 1, the output divide-by-2 function is chosen. when it is set to 0, normal operation occurs. divide-by-2 select db23 is the divide-by-2 select bit. when programmed to 1, the divide-by-2 output is selected as the prescaler input. when set to 0, the fundamental is used as the prescaler input. for exam- ple, using the output divide-by-2 feature and a pfd frequency of 200 khz, the user needs a value of n = 13,000 to generate 1,500 mhz. with the divide-by-2 select bit high, the user may keep n = 6,500. r counter latch with (c2, c1) = (0, 1), the r counter latch is programmed. table 9 shows the input data format for programming the r counter latch. r counter r1 to r14 set the counter divide ratio. the divide range is 1 (00......001) to 16383 (111......111). antibacklash pulse width db16 and db17 set the antibacklash pulse width. lock detect precision db18 is the lock detect precision bit. this bit sets the number of reference cycles with less than 15 ns phase error for entering the locked state. with ldp at 1, five cycles are taken; with ldp at 0, three cycles are taken. test mode bit db19 is the test mode bit (tmb) and should be set to 0. with tmb = 0, the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch, r counter latch, and n counter latch. note that test modes are for factory testing only and should not be pro- grammed by the user. band select clock these bits set a divider for the band select logic clock input. the output of the r counter is by default the value used to clock the band select logic, but, if this value is too high (>1 mhz), a divider can be switched on to divide the r counter output to a smaller value (see table 9). reserved bits db23 to db22 are spare bits that are reserved. they should be programmed to 0.
adf4360-0 data sheet rev. b | page 20 of 24 applications fixed frequency lo figure 17 shows the adf4360-0 used as a fixed frequency lo at 2.6 ghz. the low-pass filter was designed using adisimpll for a channel spacing of 8 mhz and an open-loop bandwidth of 40 khz. the maximum pfd frequency of the adf4360-0 is 8 mhz. because using a larger pfd frequency allows users to use a smaller n, the in-band phase noise is reduced to as low as possible, C100 dbc/hz. the 40 khz bandwidth is chosen to be just greater than the point at which the open-loop phase noise of the vco is C100 dbc/hz, thus giving the best possible integrated noise. the typical rms phase noise (100 hz to 100 khz) of the lo in this configuration is 0.35. the reference frequency is from a 16 mhz tcxo from fox; thus, an r value of 2 is programmed. taking into account the high pfd frequency and its effect on the band select logic, the band select clock divider is enabled. in this case, a value of 8 is chosen. a very simple pull-up resistor and dc blocking capacitor complete the rf output stage. spi compatible serial bus adf4360-0 v vco v vco fox 801be-160 16mhz v vco cpgnd agnd dgnd rf out b rf out a cp 1nf 560pf 270pf 8.2nf 51 51 51 100pf 100pf 1nf1nf 10 f 4.7k 1.5k 3k r set c c le data clk ref in c n v tune dv dd av dd ce muxout 5 4 24 7 20 23 2 21 6 14 16 17 18 19 13 1 12 v vdd lock detect 04644-021 3 8 9 10 11 22 15 figure 17. fixed frequency lo interfacing the adf4360 family has a simple spi?-compatible serial interface for writing to the device. clk, data, and le control the data transfer. when le goes high, the 24 bits that have been clocked into the appropriate register on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 5 for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible is 833 khz or one update every 1.2 s. this is more than adequate for systems that have typical lock times in hundreds of microseconds. aduc812 interface figure 18 shows the interface between the adf4360 family and the aduc812 microconverter?. because the aduc812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4360 family needs a 24-bit word, which is accomplished by writing three 8- bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. 04644-022 aduc812 adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi i/o ports figure 18. aduc812 to adf4360-x interface i/o port lines on the aduc812 are also used to control power- down (ce input) and detect lock (muxout configured as lock detect and polled by the port input). when operating in the described mode, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 166 khz. adsp-21xx interface figure 19 shows the interface between the adf4360 family and the adsp-21xx digital signal processor. the adf4360 family needs a 24-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. 04644-023 adsp-21xx adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi tfs i/o ports figure 19. adsp-21xx to adf4360-x interface set up the word length for 8 bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer.
data sheet adf4360-0 rev. b | page 21 of 24 pcb design guidelines for chip scale package the leads on the chip scale package (cp-24) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package lead length and 0.05 mm wider than the package lead width. the lead should be centered on the pad to ensure that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via. the user should connect the printed circuit thermal pad to agnd. this is internally connected to agnd. output matching there are a number of ways to match the output of the adf4360-0 for optimum operation; the most basic is to use a 50 resistor to v vco . a dc bypass capacitor of 100 pf is connected in series, as shown in figure 20 . because the resistor is not frequency dependent, this provides a good broadband match. the output power in this circuit typically gives ?6.5 dbm output power into a 50 load. 100pf 04644-024 rf out v vco 50 51 figure 20. simple adf4360-1 output stage a better solution is to use a shunt inductor (acting as an rf choke) to v vco . this gives a better match than a resistor and, therefore, more output power. additionally, a series inductor is added after the dc bypass capacitor to provide a resonant lc circuit. this tunes the oscillator output and provides approximately 10 db additional rejection of the second harmonic. the shunt inductor needs to be a relatively low value (<10 nh). experiments have shown that the circuit shown in figure 21 provides an excellent match to 50 over the operating range of the adf4360-0. this gives approximately ?4 dbm output power across the frequency range of the adf4360-0. both single-ended architectures can be examined using the ev-adf4360-0eb1 evaluation board. 3.9nh 47nh 1.5pf 04644-025 rf out v vco 50 figure 21. differential adf4360-0 output stage if the user does not need the differential outputs available on the adf4360-0, the user may either terminate the unused output or combine both outputs using a balun. the circuit in figure 22 shows how best to combine the outputs. 1nh 3.6nh 47nh 3.6nh 1.5pf 10pf 1.5pf 50 1nh rf out a v vco rf out b 04644-026 figure 22. balun for combining adf4360-0 rf outputs the circuit in figure 22 is a lumped-lattice-type lc balun. it is designed for a center frequency of 2.6 ghz and outputs ?1 dbm at this frequency. the series 1 nh inductor is used to tune out any parasitic capacitance due to the board layout from each input, and the remainder of the circuit is used to shift the output of one rf input by +90 and the second by ?90, thus combining the two. the action of the 3.6 nh inductor and the 1.5 pf capacitor accomplishes this. the 12 nh is used to provide an rf choke to feed the supply voltage, and the 10 pf capacitor provides the necessary dc block. to ensure good rf performance, the circuits in figure 20 and figure 22 are implemented with coilcraft 0402/0603 inductors and avx 0402 thin-film capacitors. alternatively, instead of the lc balun shown in figure 22 , both outputs may be combined using a 180 rat-race coupler.
adf4360-0 data sheet rev. b | page 22 of 24 outline dimensions compliant to jedec standards mo-220-vggd-2 08-18-2010-a 1 0.50 bsc p i n 1 i n d i c a t o r 2.50 bcs 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ seating plane coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 0.20 min 2.45 2.30 sq 2.15 24 7 19 12 13 18 6 (bottom view) 0.60 max 0.60 max pin 1 indicator 4.10 4.00 sq 3.90 3.75 bsc sq exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 23. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-2) dimensions shown in millimeters ordering guide model 1 temperature range frequency range package description package option adf4360-0bcpz ?40c to +85c 2400 mhz to 2725 mhz 24-lead lfcsp_vq cp-24-2 adf4360-0bcpzrl ?40c to +85c 2400 mhz to 2725 mhz 24-lead lfcsp_vq cp-24-2 adf4360-0bcpzrl7 ?40c to +85c 2400 mhz to 2725 mhz 24-lead lfcsp_vq cp-24-2 EV-ADF4360-0EB1Z evaluation board 1 z = rohs compliant part.
data sheet adf4360-0 rev. b | page 23 of 24 notes
adf4360-0 data sheet rev. b | page 24 of 24 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2004C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04644-0-2/12(b)

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